Contents

Architecture Components

• 16-bit Modified Shift Register
• 3-bit Up Counter
• 8-bit Subtracter (ALU)
• 8-bit Ripple Carry Adder Unit
• 1-bit Adder Unit
• ALU using carry look-ahead logic (too big to fit on chip)
  • 8-bit Adder/Subtracter (ALU)
  • 8-bit Carry Look-ahead Adder
  • 1-bit Adder Unit

Architecture Design

General Overview of Architecture:

Symbol:

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16-bit Modified Shift Register (updated 4/13/1998)
Characteristics: Remainder is computed in high byte, quotient is computed in low byte. ALU feeds the high byte. clk -- clock, rising edge RQ_LOAD -- updates RQ16 register with inputs !FINISHED !ALUcout -- Left shift 0 ALUcout -- Left shift 1, load ALU[6..0] into RQ[15..9] FINISHED !ALUcout -- Store 0 into RQ[0] and RQ[15], left shift RQ[6..0] into RQ[7..1], RQ[14..8] remains constant ALUcout -- Store 1 into RQ[0], left shift RQ[6..0] into RQ[7..1], load ALU[6..0] into RQ[14..8], store 0 into RQ[15] RQ_INIT -- load Din[7..0] into RQ[8..1], clear rest of RQ Data Inputs -- Dividend[7..0], ALU[7..0] Data Outputs -- R ( RQ[15..8]) and Q ( RQ[7..0] )
MaxPlus+2 Files	Symbol
AHDL source
Simulation source
Report file
Symbol file

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3-bit Up Counter (updated 4/11/1998)
Characteristics: 3-bit up counter is used to track the shifting of the dividend. Since the architecture is clocked on the same edge as the C/U, the output O7 is monitored. clk -- clock, rising edge CNT_CLR -- clears counter UP -- increments counter Data Outputs -- C[2..0]
MaxPlus+2 Files	Symbol
AHDL source
Simulation source
Report file
Symbol file

[ Contents ] [ Design ]

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8-bit Subtracter (ALU) (updated 4/13/1998)
Characteristics: 8-bit subtracter (ALU) is used to perform subtraction of 8-bit numbers. This unit uses the X input and complemented input of the Y input as input to the 8-bit adder described next. A logic high is fed into the carry in on the 8-bit adder. There are no provisions for overflow or underflow correction. Data Inputs -- X[7..0], Y[7..0] Data Outputs -- S[7..0]
MaxPlus+2 Files	Symbol
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Simulation source
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8-bit Adder unit (updated 4/13/1998)
Characteristics: A component of the 8-bit ALU. It is composed of eight 1-bit adder units serially connected to form an 8-bit ripple carry adder bit used by the ALU. Data Inputs -- X[7..0], Y[7..0] Data Outputs -- S[7..0], Cout
MaxPlus+2 Files	Symbol
Graphics editor file
Simulation source
Report file
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Simulation Waveform
Propagation Delay

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1-bit Adder unit (updated 4/11/1998)
Characteristics: A component of the 8-bit ALU. The 1-bit adder is used to determine the sum bit and the carry bit used by the ALU. It uses two-level logic and participates in a ripple carry configuration. (Reference Nelson(1995), pp 313.) Data Inputs -- A, B, Cin Data Outputs -- S, Cout
MaxPlus+2 Files	Symbol
Graphics editor file
Simulation source
Report file
Symbol file

[ Contents ] [ Design ]

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Created 4/10/1998
Last modified 4/23/1998