Project Informationj:\odu\ece\ece 341\project\website\current\components\divider.rpt

MAX+plus II Compiler Report File
Version 7.21 Student Edition
Compiled: 04/24/98 17:03:41

Copyright (C) 1991-1997 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

divider   EPM7128SLC84-7   19       18       0      45      31          35 %

User Pins:                 19       18       0  



Project Informationj:\odu\ece\ece 341\project\website\current\components\divider.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'clock' chosen for auto global Clock


Project Informationj:\odu\ece\ece 341\project\website\current\components\divider.rpt

** STATE MACHINE ASSIGNMENTS **


|control:26|ss: MACHINE
        OF BITS (
           |control:26|ss~2,
           |control:26|ss~1
        )
        WITH STATES (
                            wait = B"00", 
                            div0 = B"11", 
                            loop = B"10", 
                          finish = B"01"
);



Project Informationj:\odu\ece\ece 341\project\website\current\components\divider.rpt

** FILE HIERARCHY **



|arch:25|
|arch:25|alu8:49|
|arch:25|alu8:49|adder8:48|
|arch:25|alu8:49|adder8:48|adder:25|
|arch:25|alu8:49|adder8:48|adder:34|
|arch:25|alu8:49|adder8:48|adder:31|
|arch:25|alu8:49|adder8:48|adder:30|
|arch:25|alu8:49|adder8:48|adder:29|
|arch:25|alu8:49|adder8:48|adder:28|
|arch:25|alu8:49|adder8:48|adder:27|
|arch:25|alu8:49|adder8:48|adder:26|
|arch:25|rq16:55|
|arch:25|up3:60|
|control:26|


Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

***** Logic for device 'divider' compiled without errors.




Device: EPM7128SLC84-7
Turbo: ON
Security: OFF

Device Options:
    Enable JTAG Support                        = ON
    JTAG User Code                             = ffff
                                                                              
                  D  D  D     D  D  D                       R  R              
                  i  i  i     i  i  i                       E  E              
                  v  v  v     v  v  v  V                    S  S              
                  i  i  i     i  i  i  C           c        E  E  V     E     
                  s  s  s     s  s  s  C           l     D  R  R  C     R     
               D  o  o  o  G  o  o  o  I  G  G  G  o  G  O  V  V  C     R     
               I  r  r  r  N  r  r  r  N  N  N  N  c  N  N  E  E  I  R  O  R  
               V  5  4  2  D  1  0  3  T  D  D  D  k  D  E  D  D  O  5  R  4  
             -----------------------------------------------------------------_ 
           /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
 Divisor7 | 12                                                              74 | R7 
    VCCIO | 13                                                              73 | R6 
     #TDI | 14                                                              72 | GND 
Dividend3 | 15                                                              71 | #TDO 
Dividend2 | 16                                                              70 | Q4 
Dividend1 | 17                                                              69 | Q3 
Dividend0 | 18                                                              68 | Q0 
      GND | 19                                                              67 | RESERVED 
 Divisor6 | 20                                                              66 | VCCIO 
    RESET | 21                                                              65 | Q1 
 RESERVED | 22                        EPM7128SLC84-7                        64 | Q2 
     #TMS | 23                                                              63 | Q5 
 RESERVED | 24                                                              62 | #TCK 
 RESERVED | 25                                                              61 | Q7 
    VCCIO | 26                                                              60 | R1 
Dividend6 | 27                                                              59 | GND 
 RESERVED | 28                                                              58 | R3 
Dividend5 | 29                                                              57 | R2 
 RESERVED | 30                                                              56 | Q6 
Dividend4 | 31                                                              55 | RESERVED 
      GND | 32                                                              54 | R0 
          |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
            ------------------------------------------------------------------ 
               R  R  R  R  R  V  R  R  D  G  V  R  R  R  G  R  R  R  R  R  V  
               E  E  E  E  E  C  E  E  i  N  C  E  E  E  N  E  E  E  E  E  C  
               S  S  S  S  S  C  S  S  v  D  C  S  S  S  D  S  S  S  S  S  C  
               E  E  E  E  E  I  E  E  i     I  E  E  E     E  E  E  E  E  I  
               R  R  R  R  R  O  R  R  d     N  R  R  R     R  R  R  R  R  O  
               V  V  V  V  V     V  V  e     T  V  V  V     V  V  V  V  V     
               E  E  E  E  E     E  E  n        E  E  E     E  E  E  E  E     
               D  D  D  D  D     D  D  d        D  D  D     D  D  D  D  D     
                                       7                                      


N.C. = Not Connected.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 or 5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which will be tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary Scan Testing Pin.


Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   8/ 8(100%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     0/16(  0%)   7/ 8( 87%)   0/16(  0%)   0/36(  0%) 
C:    LC33 - LC48     0/16(  0%)   4/ 8( 50%)   0/16(  0%)   0/36(  0%) 
D:    LC49 - LC64     1/16(  6%)   1/ 8( 12%)   0/16(  0%)  15/36( 41%) 
E:    LC65 - LC80     4/16( 25%)   0/ 8(  0%)  10/16( 62%)  12/36( 33%) 
F:    LC81 - LC96     9/16( 56%)   7/ 8( 87%)  16/16(100%)  27/36( 75%) 
G:   LC97 - LC112    15/16( 93%)   7/ 8( 87%)  15/16( 93%)  30/36( 83%) 
H:  LC113 - LC128    16/16(100%)   6/ 8( 75%)  13/16( 81%)  28/36( 77%) 


Total dedicated input pins used:                 1/4      ( 25%)
Total I/O pins used:                            40/64     ( 62%)
Total logic cells used:                         45/128    ( 35%)
Total shareable expanders used:                 31/128    ( 24%)
Total Turbo logic cells used:                   45/128    ( 35%)
Total shareable expanders not available (n/a):  23/128    ( 17%)
Average fan-in:                                  8.82
Total fan-in:                                   397

Total input pins required:                      19
Total input registers required:                  0
Total output pins required:                     18
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     45
Total flipflops required:                       21
Total pterms required:                         224
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          22

Synthesized logic cells:                        19/ 128   ( 14%)



Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  83      -   -       INPUT              0      0   0    0    0    0    0  clock
  11    (5)  (A)      INPUT              0      0   0    0    0   14    7  DIV
  18   (24)  (B)      INPUT              0      0   0    0    0    1    0  Dividend0
  17   (25)  (B)      INPUT              0      0   0    0    0    1    0  Dividend1
  16   (27)  (B)      INPUT              0      0   0    0    0    1    0  Dividend2
  15   (29)  (B)      INPUT              0      0   0    0    0    1    0  Dividend3
  31   (35)  (C)      INPUT              0      0   0    0    0    1    0  Dividend4
  29   (38)  (C)      INPUT              0      0   0    0    0    1    0  Dividend5
  27   (43)  (C)      INPUT              0      0   0    0    0    1    0  Dividend6
  41   (49)  (D)      INPUT              0      0   0    0    0    1    0  Dividend7
   5   (14)  (A)      INPUT              0      0   0    0    0    1    9  Divisor0
   6   (13)  (A)      INPUT              0      0   0    0    0    0    8  Divisor1
   8   (11)  (A)      INPUT              0      0   0    0    0    0    6  Divisor2
   4   (16)  (A)      INPUT              0      0   0    0    0    0    6  Divisor3
   9    (8)  (A)      INPUT              0      0   0    0    0    1   11  Divisor4
  10    (6)  (A)      INPUT              0      0   0    0    0    0    8  Divisor5
  20   (21)  (B)      INPUT              0      0   0    0    0    2    6  Divisor6
  12    (3)  (A)      INPUT              0      0   0    0    0    7   13  Divisor7
  21   (19)  (B)      INPUT              0      0   0    0    0    0    2  RESET


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  81    128    H     OUTPUT     t        0      0   0    0    2    0    0  DONE
  76    120    H     OUTPUT     t        0      0   0    0    2    0    0  ERROR
  68    105    G         FF  +  t        0      0   0    2    5    2    0  Q0
  65    101    G         FF  +  t        0      0   0    2    4    2    0  Q1
  64     99    G         FF  +  t        0      0   0    2    4    2    0  Q2
  69    107    G         FF  +  t        0      0   0    2    4    2    0  Q3
  70    109    G         FF  +  t        0      0   0    2    4    2    0  Q4
  63     97    G         FF  +  t        0      0   0    2    4    2    0  Q5
  56     86    F         FF  +  t        0      0   0    2    4    2    0  Q6
  61     94    F         FF  +  t        0      0   0    2    4    2    0  Q7
  54     83    F         FF  +  t        7      3   1    4    9    1    8  R0
  60     93    F         FF  +  t        0      0   0    1    5    1    7  R1
  57     88    F         FF  +  t        4      3   1    2   10    2    5  R2
  58     91    F         FF  +  t        5      4   1    1   11    1    5  R3
  75    118    H         FF  +  t        0      0   0    1    5    2    9  R4
  77    123    H         FF  +  t        6      5   1    3   13    1    7  R5
  73    115    H         FF  +  t        0      0   0    2    9    1    4  R6
  74    117    H         FF  +  t        4      3   1    3    7    7   12  R7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -     84    F        XOR     t        2      0   0    3    3    2    0  |arch:25|alu8:49|adder8:48|adder:27|:33
   -     90    F        XOR     t        4      0   1    3    3    0    2  |arch:25|alu8:49|adder8:48|adder:27|:38
   -    103    G        OR2   s t        1      0   1    4    4    1    9  |arch:25|alu8:49|adder8:48|adder:28|~38~1
   -    102    G        OR2   s t        1      0   1    4    4    1    9  |arch:25|alu8:49|adder8:48|adder:28|~38~2
 (67)   104    G       SOFT   s t        1      0   1    4    4    1    9  |arch:25|alu8:49|adder8:48|adder:30|~38~1
 (48)    72    E        XOR     t !      4      0   1    2    5    2    2  |arch:25|alu8:49|adder8:48|adder:30|:38
 (79)   125    H        OR2   s t        2      1   1    4    6    0    1  |arch:25|alu8:49|adder8:48|adder:34|~38~1
   -    119    H        OR2   s t        2      1   1    2    6    0    1  |arch:25|alu8:49|adder8:48|adder:34|~38~2
   -    116    H        OR2   s t        2      1   1    3    5    0    1  |arch:25|alu8:49|adder8:48|adder:34|~38~3
   -    122    H        OR2   s t !      0      0   0    2    5    7   11  |arch:25|alu8:49|adder8:48|adder:34|~38~4
   -    111    G        OR2   s t !      2      1   1    2    6    1    0  |arch:25|rq16:55|~207~1
   -    110    G        XOR   s t        6      2   1    3    7    1    0  |arch:25|rq16:55|~207~2
   -    100    G        XOR   s t        2      1   1    3    4    1    0  |arch:25|rq16:55|~207~3
   -    108    G       SOFT   s t        3      2   1    3    9    1    0  |arch:25|rq16:55|~255~1
   -     98    G        XOR   s t        5      3   1    2    7    1    0  |arch:25|rq16:55|~270~1
   -    113    H        OR2   s t        4      3   1    2    9    1    0  |arch:25|rq16:55|~270~2
   -     68    E        OR2   s t        3      2   1    3    7    0    1  |arch:25|rq16:55|~291~1
 (49)    73    E        OR2   s t        2      1   1    3    6    0    1  |arch:25|rq16:55|~291~2
   -     79    E        XOR   s t        3      1   0    2    7    0    2  |arch:25|rq16:55|~291~3
   -    127    H       SOFT   s t        3      3   0    2   12    1    0  |arch:25|rq16:55|~297~1
 (80)   126    H        OR2   s t        2      1   1    3   10    1    0  |arch:25|rq16:55|~318~1
   -    124    H       SOFT   s t        1      1   0    2    9    1    0  |arch:25|rq16:55|~334~1
   -     81    F       TFFE  +  t        0      0   0    1    2    5   12  |arch:25|up3:60|uc0
   -    114    H       DFFE  +  t        1      0   1    1    4    5   12  |arch:25|up3:60|uc1
   -    121    H       TFFE  +  t        0      0   0    1    4    5   10  |arch:25|up3:60|uc2
   -     62    D       TFFE  +  t        0      0   0   10    5   18    9  |control:26|ss~1
   -    106    G       DFFE  +  t        0      0   0    2    5   18    9  |control:26|ss~2


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

           Logic cells placed in LAB 'D'
        +- LC62 |control:26|ss~1
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'D'
LC      | | A B C D E F G H |     Logic cells that feed LAB 'D':
LC62 -> * | - - - * - * * * | <-- |control:26|ss~1

Pin
83   -> - | - - - - - - - - | <-- clock
11   -> * | - - - * - * * * | <-- DIV
5    -> * | - - - * - * * - | <-- Divisor0
6    -> * | - - - * - * * - | <-- Divisor1
8    -> * | - - - * - * * - | <-- Divisor2
4    -> * | - - - * - - * - | <-- Divisor3
9    -> * | - - - * * - - * | <-- Divisor4
10   -> * | - - - * * - - * | <-- Divisor5
20   -> * | - - - * - - - * | <-- Divisor6
12   -> * | - - - * * * * * | <-- Divisor7
21   -> * | - - - * - - * - | <-- RESET
LC81 -> * | - - - * - * * * | <-- |arch:25|up3:60|uc0
LC114-> * | - - - * - * * * | <-- |arch:25|up3:60|uc1
LC121-> * | - - - * - * * * | <-- |arch:25|up3:60|uc2
LC106-> * | - - - * - * * * | <-- |control:26|ss~2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                 Logic cells placed in LAB 'E'
        +------- LC72 |arch:25|alu8:49|adder8:48|adder:30|:38
        | +----- LC68 |arch:25|rq16:55|~291~1
        | | +--- LC73 |arch:25|rq16:55|~291~2
        | | | +- LC79 |arch:25|rq16:55|~291~3
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'E'
LC      | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':
LC68 -> - - - * | - - - - * - - - | <-- |arch:25|rq16:55|~291~1
LC73 -> - - - * | - - - - * - - - | <-- |arch:25|rq16:55|~291~2

Pin
83   -> - - - - | - - - - - - - - | <-- clock
9    -> * * * * | - - - * * - - * | <-- Divisor4
10   -> * * * * | - - - * * - - * | <-- Divisor5
12   -> - * * - | - - - * * * * * | <-- Divisor7
LC103-> * * * * | - - - - * - - * | <-- |arch:25|alu8:49|adder8:48|adder:28|~38~1
LC102-> * * * * | - - - - * - - * | <-- |arch:25|alu8:49|adder8:48|adder:28|~38~2
LC104-> * * * * | - - - - * - - * | <-- |arch:25|alu8:49|adder8:48|adder:30|~38~1
LC122-> - * * - | - - - - * * * * | <-- |arch:25|alu8:49|adder8:48|adder:34|~38~4
LC118-> * * * * | - - - - * - - * | <-- R4
LC123-> * * - * | - - - - * - - * | <-- R5
LC117-> - * * - | - - - - * * * * | <-- R7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                           Logic cells placed in LAB 'F'
        +----------------- LC84 |arch:25|alu8:49|adder8:48|adder:27|:33
        | +--------------- LC90 |arch:25|alu8:49|adder8:48|adder:27|:38
        | | +------------- LC81 |arch:25|up3:60|uc0
        | | | +----------- LC86 Q6
        | | | | +--------- LC94 Q7
        | | | | | +------- LC83 R0
        | | | | | | +----- LC93 R1
        | | | | | | | +--- LC88 R2
        | | | | | | | | +- LC91 R3
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':
LC84 -> - - - - - - - * * | - - - - - * - - | <-- |arch:25|alu8:49|adder8:48|adder:27|:33
LC81 -> - - * - - * - * * | - - - * - * * * | <-- |arch:25|up3:60|uc0
LC86 -> - - - * * - - - - | - - - - - * - - | <-- Q6
LC94 -> - - - - * * - - - | - - - - - * - - | <-- Q7
LC83 -> * * - - - * - - - | - - - - - * * - | <-- R0
LC93 -> * * - - - - * - - | - - - - - * * - | <-- R1
LC88 -> * * - - - - - * * | - - - - - * * - | <-- R2
LC91 -> - - - - - - - - * | - - - - - * * - | <-- R3

Pin
83   -> - - - - - - - - - | - - - - - - - - | <-- clock
11   -> - - * * * * * * - | - - - * - * * * | <-- DIV
29   -> - - - * - - - - - | - - - - - * - - | <-- Dividend5
27   -> - - - - * - - - - | - - - - - * - - | <-- Dividend6
41   -> - - - - - * - - - | - - - - - * - - | <-- Dividend7
5    -> * * - - - * - - - | - - - * - * * - | <-- Divisor0
6    -> * * - - - - - - - | - - - * - * * - | <-- Divisor1
8    -> * * - - - - - - - | - - - * - * * - | <-- Divisor2
12   -> - - - - - * - * * | - - - * * * * * | <-- Divisor7
LC122-> - - - - - * - * * | - - - - * * * * | <-- |arch:25|alu8:49|adder8:48|adder:34|~38~4
LC111-> - - - - - - * - - | - - - - - * - - | <-- |arch:25|rq16:55|~207~1
LC110-> - - - - - - * - - | - - - - - * - - | <-- |arch:25|rq16:55|~207~2
LC100-> - - - - - - - * - | - - - - - * - - | <-- |arch:25|rq16:55|~207~3
LC108-> - - - - - - - - * | - - - - - * - - | <-- |arch:25|rq16:55|~255~1
LC114-> - - - - - * - * * | - - - * - * * * | <-- |arch:25|up3:60|uc1
LC121-> - - - - - * - * * | - - - * - * * * | <-- |arch:25|up3:60|uc2
LC62 -> - - * * * * * * * | - - - * - * * * | <-- |control:26|ss~1
LC106-> - - * * * * * * * | - - - * - * * * | <-- |control:26|ss~2
LC97 -> - - - * - - - - - | - - - - - * * - | <-- Q5
LC117-> - - - - - * - * * | - - - - * * * * | <-- R7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                                       Logic cells placed in LAB 'G'
        +----------------------------- LC103 |arch:25|alu8:49|adder8:48|adder:28|~38~1
        | +--------------------------- LC102 |arch:25|alu8:49|adder8:48|adder:28|~38~2
        | | +------------------------- LC104 |arch:25|alu8:49|adder8:48|adder:30|~38~1
        | | | +----------------------- LC111 |arch:25|rq16:55|~207~1
        | | | | +--------------------- LC110 |arch:25|rq16:55|~207~2
        | | | | | +------------------- LC100 |arch:25|rq16:55|~207~3
        | | | | | | +----------------- LC108 |arch:25|rq16:55|~255~1
        | | | | | | | +--------------- LC98 |arch:25|rq16:55|~270~1
        | | | | | | | | +------------- LC106 |control:26|ss~2
        | | | | | | | | | +----------- LC105 Q0
        | | | | | | | | | | +--------- LC101 Q1
        | | | | | | | | | | | +------- LC99 Q2
        | | | | | | | | | | | | +----- LC107 Q3
        | | | | | | | | | | | | | +--- LC109 Q4
        | | | | | | | | | | | | | | +- LC97 Q5
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC106-> - - - - - - * - * * * * * * * | - - - * - * * * | <-- |control:26|ss~2
LC105-> - - - - - - - - - * * - - - - | - - - - - - * - | <-- Q0
LC101-> - - - - - - - - - - * * - - - | - - - - - - * - | <-- Q1
LC99 -> - - - - - - - - - - - * * - - | - - - - - - * - | <-- Q2
LC107-> - - - - - - - - - - - - * * - | - - - - - - * - | <-- Q3
LC109-> - - - - - - - - - - - - - * * | - - - - - - * - | <-- Q4
LC97 -> - - - - - - - - - - - - - - * | - - - - - * * - | <-- Q5

Pin
83   -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- clock
11   -> - - - - - - * - * * * * * * * | - - - * - * * * | <-- DIV
18   -> - - - - - - - - - - * - - - - | - - - - - - * - | <-- Dividend0
17   -> - - - - - - - - - - - * - - - | - - - - - - * - | <-- Dividend1
16   -> - - - - - - - - - - - - * - - | - - - - - - * - | <-- Dividend2
15   -> - - - - - - - - - - - - - * - | - - - - - - * - | <-- Dividend3
31   -> - - - - - - - - - - - - - - * | - - - - - - * - | <-- Dividend4
5    -> * * * * * * - - - - - - - - - | - - - * - * * - | <-- Divisor0
6    -> * * * - * * - - - - - - - - - | - - - * - * * - | <-- Divisor1
8    -> * * * - - - - - - - - - - - - | - - - * - * * - | <-- Divisor2
4    -> * * * - - - * * - - - - - - - | - - - * - - * - | <-- Divisor3
12   -> - - - * * * * * - * - - - - - | - - - * * * * * | <-- Divisor7
21   -> - - - - - - - - * - - - - - - | - - - * - - * - | <-- RESET
LC90 -> - - - - - - * * - - - - - - - | - - - - - - * - | <-- |arch:25|alu8:49|adder8:48|adder:27|:38
LC122-> - - - * * * * * - * - - - - - | - - - - * * * * | <-- |arch:25|alu8:49|adder8:48|adder:34|~38~4
LC81 -> - - - * * - * * * - - - - - - | - - - * - * * * | <-- |arch:25|up3:60|uc0
LC114-> - - - * * - * * * - - - - - - | - - - * - * * * | <-- |arch:25|up3:60|uc1
LC121-> - - - * * - * * * - - - - - - | - - - * - * * * | <-- |arch:25|up3:60|uc2
LC62 -> - - - - - - * - * * * * * * * | - - - * - * * * | <-- |control:26|ss~1
LC83 -> * * * * * * - - - - - - - - - | - - - - - * * - | <-- R0
LC93 -> * * * - * * - - - - - - - - - | - - - - - * * - | <-- R1
LC88 -> * * * - - - - - - - - - - - - | - - - - - * * - | <-- R2
LC91 -> * * * - - - * * - - - - - - - | - - - - - * * - | <-- R3
LC117-> - - - * * * * * - * - - - - - | - - - - * * * * | <-- R7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                         Logic cells placed in LAB 'H'
        +------------------------------- LC125 |arch:25|alu8:49|adder8:48|adder:34|~38~1
        | +----------------------------- LC119 |arch:25|alu8:49|adder8:48|adder:34|~38~2
        | | +--------------------------- LC116 |arch:25|alu8:49|adder8:48|adder:34|~38~3
        | | | +------------------------- LC122 |arch:25|alu8:49|adder8:48|adder:34|~38~4
        | | | | +----------------------- LC113 |arch:25|rq16:55|~270~2
        | | | | | +--------------------- LC127 |arch:25|rq16:55|~297~1
        | | | | | | +------------------- LC126 |arch:25|rq16:55|~318~1
        | | | | | | | +----------------- LC124 |arch:25|rq16:55|~334~1
        | | | | | | | | +--------------- LC114 |arch:25|up3:60|uc1
        | | | | | | | | | +------------- LC121 |arch:25|up3:60|uc2
        | | | | | | | | | | +----------- LC128 DONE
        | | | | | | | | | | | +--------- LC120 ERROR
        | | | | | | | | | | | | +------- LC118 R4
        | | | | | | | | | | | | | +----- LC123 R5
        | | | | | | | | | | | | | | +--- LC115 R6
        | | | | | | | | | | | | | | | +- LC117 R7
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC125-> - - - * - - - - - - - - - - - - | - - - - - - - * | <-- |arch:25|alu8:49|adder8:48|adder:34|~38~1
LC119-> - - - * - - - - - - - - - - - - | - - - - - - - * | <-- |arch:25|alu8:49|adder8:48|adder:34|~38~2
LC116-> - - - * - - - - - - - - - - - - | - - - - - - - * | <-- |arch:25|alu8:49|adder8:48|adder:34|~38~3
LC122-> - - - - * * * * - - - - - * * * | - - - - * * * * | <-- |arch:25|alu8:49|adder8:48|adder:34|~38~4
LC113-> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- |arch:25|rq16:55|~270~2
LC127-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- |arch:25|rq16:55|~297~1
LC126-> - - - - - - - - - - - - - - * - | - - - - - - - * | <-- |arch:25|rq16:55|~318~1
LC124-> - - - - - - - - - - - - - - - * | - - - - - - - * | <-- |arch:25|rq16:55|~334~1
LC114-> - - - - * * * * * * - - - * * - | - - - * - * * * | <-- |arch:25|up3:60|uc1
LC121-> - - - - * * * * - * - - - * * - | - - - * - * * * | <-- |arch:25|up3:60|uc2
LC118-> - * * * * * - - - - - - * * - - | - - - - * - - * | <-- R4
LC123-> * * * * - - - - - - - - - * - - | - - - - * - - * | <-- R5
LC115-> * * - - - - * * - - - - - - * * | - - - - - - - * | <-- R6
LC117-> * - - - * * * * - - - - - * * * | - - - - * * * * | <-- R7

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clock
11   -> - - - - - - * - * * - - * * - * | - - - * - * * * | <-- DIV
9    -> * * * * * * - - - - - - - * - - | - - - * * - - * | <-- Divisor4
10   -> * * * - - - - - - - - - - - - - | - - - * * - - * | <-- Divisor5
20   -> * - * * - - * * - - - - - - * * | - - - * - - - * | <-- Divisor6
12   -> * - - - * * * * - - - - - * * * | - - - * * * * * | <-- Divisor7
LC103-> * * * - * * - - - - - - - * - - | - - - - * - - * | <-- |arch:25|alu8:49|adder8:48|adder:28|~38~1
LC102-> * * * - * * - - - - - - - * - - | - - - - * - - * | <-- |arch:25|alu8:49|adder8:48|adder:28|~38~2
LC104-> * * * - * * - - - - - - - * - - | - - - - * - - * | <-- |arch:25|alu8:49|adder8:48|adder:30|~38~1
LC72 -> - - - - - - * * - - - - - - * * | - - - - - - - * | <-- |arch:25|alu8:49|adder8:48|adder:30|:38
LC98 -> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- |arch:25|rq16:55|~270~1
LC79 -> - - - - - * * - - - - - - - - - | - - - - - - - * | <-- |arch:25|rq16:55|~291~3
LC81 -> - - - - * * * * * * - - - * * - | - - - * - * * * | <-- |arch:25|up3:60|uc0
LC62 -> - - - - - * * * * * * * * * * * | - - - * - * * * | <-- |control:26|ss~1
LC106-> - - - - - * * * * * * * * * * * | - - - * - * * * | <-- |control:26|ss~2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:j:\odu\ece\ece 341\project\website\current\components\divider.rpt
divider

** EQUATIONS **

clock    : INPUT;
DIV      : INPUT;
Dividend0 : INPUT;
Dividend1 : INPUT;
Dividend2 : INPUT;
Dividend3 : INPUT;
Dividend4 : INPUT;
Dividend5 : INPUT;
Dividend6 : INPUT;
Dividend7 : INPUT;
Divisor0 : INPUT;
Divisor1 : INPUT;
Divisor2 : INPUT;
Divisor3 : INPUT;
Divisor4 : INPUT;
Divisor5 : INPUT;
Divisor6 : INPUT;
Divisor7 : INPUT;
RESET    : INPUT;

-- Node name is 'DONE' = '|control:26|finish' from file "control.tdf" line 23, column 46
-- Equation name is 'DONE', type is output 
 DONE    = LCELL( _EQ001 $  GND);
  _EQ001 =  _LC062 & !_LC106;

-- Node name is 'ERROR' = '|control:26|div0' from file "control.tdf" line 23, column 34
-- Equation name is 'ERROR', type is output 
 ERROR   = LCELL( _EQ002 $  GND);
  _EQ002 =  _LC062 &  _LC106;

-- Node name is 'Q0' = '|arch:25|rq16:55|rq0' from file "rq16.tdf" line 8, column 5
-- Equation name is 'Q0', type is output 
 Q0      = DFFE( _EQ003 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ003 = !Divisor7 & !_LC062 &  _LC106 &  R7
         # !_LC062 &  _LC106 &  _LC122
         #  _LC062 &  Q0
         # !DIV & !_LC106 &  Q0;

-- Node name is 'Q1' = '|arch:25|rq16:55|rq1' from file "rq16.tdf" line 8, column 5
-- Equation name is 'Q1', type is output 
 Q1      = DFFE( _EQ004 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ004 =  DIV &  Dividend0 & !_LC062 & !_LC106
         # !_LC062 &  _LC106 &  Q0
         #  _LC062 &  Q1
         # !DIV & !_LC106 &  Q1;

-- Node name is 'Q2' = '|arch:25|rq16:55|rq2' from file "rq16.tdf" line 8, column 5
-- Equation name is 'Q2', type is output 
 Q2      = DFFE( _EQ005 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ005 =  DIV &  Dividend1 & !_LC062 & !_LC106
         # !_LC062 &  _LC106 &  Q1
         #  _LC062 &  Q2
         # !DIV & !_LC106 &  Q2;

-- Node name is 'Q3' = '|arch:25|rq16:55|rq3' from file "rq16.tdf" line 8, column 5
-- Equation name is 'Q3', type is output 
 Q3      = DFFE( _EQ006 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ006 =  DIV &  Dividend2 & !_LC062 & !_LC106
         # !_LC062 &  _LC106 &  Q2
         #  _LC062 &  Q3
         # !DIV & !_LC106 &  Q3;

-- Node name is 'Q4' = '|arch:25|rq16:55|rq4' from file "rq16.tdf" line 8, column 5
-- Equation name is 'Q4', type is output 
 Q4      = DFFE( _EQ007 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ007 =  DIV &  Dividend3 & !_LC062 & !_LC106
         # !_LC062 &  _LC106 &  Q3
         #  _LC062 &  Q4
         # !DIV & !_LC106 &  Q4;

-- Node name is 'Q5' = '|arch:25|rq16:55|rq5' from file "rq16.tdf" line 8, column 5
-- Equation name is 'Q5', type is output 
 Q5      = DFFE( _EQ008 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ008 =  DIV &  Dividend4 & !_LC062 & !_LC106
         # !_LC062 &  _LC106 &  Q4
         #  _LC062 &  Q5
         # !DIV & !_LC106 &  Q5;

-- Node name is 'Q6' = '|arch:25|rq16:55|rq6' from file "rq16.tdf" line 8, column 5
-- Equation name is 'Q6', type is output 
 Q6      = DFFE( _EQ009 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ009 =  DIV &  Dividend5 & !_LC062 & !_LC106
         # !_LC062 &  _LC106 &  Q5
         #  _LC062 &  Q6
         # !DIV & !_LC106 &  Q6;

-- Node name is 'Q7' = '|arch:25|rq16:55|rq7' from file "rq16.tdf" line 8, column 5
-- Equation name is 'Q7', type is output 
 Q7      = DFFE( _EQ010 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ010 =  DIV &  Dividend6 & !_LC062 & !_LC106
         # !_LC062 &  _LC106 &  Q6
         #  _LC062 &  Q7
         # !DIV & !_LC106 &  Q7;

-- Node name is 'R0' = '|arch:25|rq16:55|rq8' from file "rq16.tdf" line 8, column 5
-- Equation name is 'R0', type is output 
 R0      = DFFE( _EQ011 $  _EQ012, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ011 =  DIV & !Dividend7 & !_LC062 & !_LC106 &  _X001 &  _X002 &  _X003
         #  _LC062 & !R0 &  _X001 &  _X002 &  _X003
         #  Divisor0 & !_LC062 &  _LC081 &  _LC106 &  _LC114 &  _LC121 &  R0 & 
              _X001 &  _X002 &  _X003 &  _X004
         # !_LC062 &  _LC106 & !Q7 &  _X001 &  _X002 &  _X003 &  _X005;
  _X001  = EXP( _LC081 &  _LC106 &  _LC114 &  _LC121 & !_LC122 & !R0 &  _X006);
  _X002  = EXP(!Divisor0 &  _LC081 &  _LC106 &  _LC114 &  _LC121 & !R0);
  _X003  = EXP(!DIV & !_LC106 & !R0);
  _X004  = EXP(!_LC122 &  _X006);
  _X005  = EXP( _LC081 &  _LC114 &  _LC121);
  _X006  = EXP(!Divisor7 &  R7);
  _EQ012 =  _X001 &  _X002 &  _X003;
  _X001  = EXP( _LC081 &  _LC106 &  _LC114 &  _LC121 & !_LC122 & !R0 &  _X006);
  _X002  = EXP(!Divisor0 &  _LC081 &  _LC106 &  _LC114 &  _LC121 & !R0);
  _X003  = EXP(!DIV & !_LC106 & !R0);
  _X006  = EXP(!Divisor7 &  R7);

-- Node name is 'R1' = '|arch:25|rq16:55|rq9' from file "rq16.tdf" line 8, column 5
-- Equation name is 'R1', type is output 
 R1      = DFFE( _EQ013 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ013 = !_LC062 &  _LC106 &  _LC111
         # !_LC062 &  _LC106 &  _LC110
         #  _LC062 &  R1
         # !DIV & !_LC106 &  R1;

-- Node name is 'R2' = '|arch:25|rq16:55|rq10' from file "rq16.tdf" line 8, column 5
-- Equation name is 'R2', type is output 
 R2      = DFFE( _EQ014 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ014 = !_LC062 &  _LC100 &  _LC106 &  _X005
         #  _LC081 &  _LC106 &  _LC114 &  _LC121 & !_LC122 &  R2 &  _X006
         # !_LC062 &  _LC081 &  _LC084 &  _LC106 &  _LC114 &  _LC121 &  _X004
         #  _LC062 &  R2
         # !DIV & !_LC106 &  R2;
  _X005  = EXP( _LC081 &  _LC114 &  _LC121);
  _X006  = EXP(!Divisor7 &  R7);
  _X004  = EXP(!_LC122 &  _X006);

-- Node name is 'R3' = '|arch:25|rq16:55|rq11' from file "rq16.tdf" line 8, column 5
-- Equation name is 'R3', type is output 
 R3      = DFFE( _EQ015 $ !_LC108, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ015 =  _LC081 & !_LC108 &  _LC114 &  _LC121 & !_LC122 & !R3 &  _X006
         # !_LC108 & !R3 &  _X007
         # !_LC062 & !_LC084 &  _LC106 & !_LC108 &  _X004 &  _X005
         # !_LC062 &  _LC106 & !_LC108 & !_LC122 & !R2 &  _X005 &  _X006;
  _X006  = EXP(!Divisor7 &  R7);
  _X007  = EXP(!_LC062 &  _LC106);
  _X004  = EXP(!_LC122 &  _X006);
  _X005  = EXP( _LC081 &  _LC114 &  _LC121);

-- Node name is 'R4' = '|arch:25|rq16:55|rq12' from file "rq16.tdf" line 8, column 5
-- Equation name is 'R4', type is output 
 R4      = DFFE( _EQ016 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ016 = !_LC062 &  _LC098 &  _LC106
         # !_LC062 &  _LC106 &  _LC113
         #  _LC062 &  R4
         # !DIV & !_LC106 &  R4;

-- Node name is 'R5' = '|arch:25|rq16:55|rq13' from file "rq16.tdf" line 8, column 5
-- Equation name is 'R5', type is output 
 R5      = DFFE( _EQ017 $ !_LC127, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ017 =  DIV & !_LC062 & !_LC106 & !_LC127
         # !Divisor4 & !_LC062 &  _LC106 & !_LC127 &  R4 &  _X004 &  _X005 & 
              _X008
         #  Divisor4 & !_LC062 & !_LC102 & !_LC103 & !_LC104 &  _LC106 & 
             !_LC127 &  R4 &  _X004 &  _X005
         # !_LC127 & !R5 &  _X007;
  _X004  = EXP(!_LC122 &  _X006);
  _X005  = EXP( _LC081 &  _LC114 &  _LC121);
  _X008  = EXP(!_LC102 & !_LC103 & !_LC104);
  _X007  = EXP(!_LC062 &  _LC106);
  _X006  = EXP(!Divisor7 &  R7);

-- Node name is 'R6' = '|arch:25|rq16:55|rq14' from file "rq16.tdf" line 8, column 5
-- Equation name is 'R6', type is output 
 R6      = TFFE( _EQ018, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ018 = !Divisor6 & !Divisor7 & !_LC062 & !_LC072 &  _LC081 &  _LC106 & 
              _LC114 &  _LC121 &  R7
         # !Divisor6 & !_LC062 & !_LC072 &  _LC081 &  _LC106 &  _LC114 & 
              _LC121 &  _LC122
         #  _LC126;

-- Node name is 'R7' = '|arch:25|rq16:55|rq15' from file "rq16.tdf" line 8, column 5
-- Equation name is 'R7', type is output 
 R7      = DFFE( _EQ019 $ !_LC124, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ019 =  DIV & !_LC062 & !_LC106 & !_LC124
         # !Divisor6 & !_LC062 & !_LC072 &  _LC106 & !_LC124 &  R6 &  _X004
         #  Divisor6 & !_LC062 &  _LC072 &  _LC106 & !_LC124 &  R6 &  _X004
         # !_LC124 & !R7 &  _X007;
  _X004  = EXP(!_LC122 &  _X006);
  _X007  = EXP(!_LC062 &  _LC106);
  _X006  = EXP(!Divisor7 &  R7);

-- Node name is '|arch:25|alu8:49|adder8:48|adder:27|:33' from file "adder.tdf" line 12, column 13
-- Equation name is '_LC084', type is buried 
_LC084   = LCELL( _EQ020 $  _EQ021);
  _EQ020 =  Divisor0 &  Divisor1 & !R0
         #  Divisor1 & !R1
         #  Divisor0 & !R0 & !R1;
  _EQ021 =  _X009 &  _X010;
  _X009  = EXP( Divisor2 &  R2);
  _X010  = EXP(!Divisor2 & !R2);

-- Node name is '|arch:25|alu8:49|adder8:48|adder:27|:38' from file "adder.tdf" line 13, column 26
-- Equation name is '_LC090', type is buried 
_LC090   = LCELL( _EQ022 $  _EQ023);
  _EQ022 =  Divisor2 & !R2 &  _X011 &  _X012 &  _X013
         #  Divisor0 &  Divisor1 & !R0 & !R2 &  _X011 &  _X012 &  _X013
         #  Divisor1 & !R1 & !R2 &  _X011 &  _X012 &  _X013
         #  Divisor0 & !R0 & !R1 & !R2 &  _X011 &  _X012 &  _X013;
  _X011  = EXP( Divisor0 &  Divisor1 &  Divisor2 & !R0);
  _X012  = EXP( Divisor1 &  Divisor2 & !R1);
  _X013  = EXP( Divisor0 &  Divisor2 & !R0 & !R1);
  _EQ023 =  _X011 &  _X012 &  _X013;
  _X011  = EXP( Divisor0 &  Divisor1 &  Divisor2 & !R0);
  _X012  = EXP( Divisor1 &  Divisor2 & !R1);
  _X013  = EXP( Divisor0 &  Divisor2 & !R0 & !R1);

-- Node name is '|arch:25|alu8:49|adder8:48|adder:28|~38~1' from file "adder.tdf" line 13, column 26
-- Equation name is '_LC103', type is buried 
-- synthesized logic cell 
_LC103   = LCELL( _EQ024 $  GND);
  _EQ024 =  Divisor0 &  Divisor1 &  Divisor2 &  Divisor3 & !R0
         #  Divisor1 &  Divisor2 &  Divisor3 & !R1
         #  Divisor2 &  Divisor3 & !R2
         #  Divisor3 & !R3
         #  Divisor2 & !R2 & !R3;

-- Node name is '|arch:25|alu8:49|adder8:48|adder:28|~38~2' from file "adder.tdf" line 13, column 26
-- Equation name is '_LC102', type is buried 
-- synthesized logic cell 
_LC102   = LCELL( _EQ025 $  GND);
  _EQ025 =  Divisor0 &  Divisor2 &  Divisor3 & !R0 & !R1
         #  Divisor0 &  Divisor1 &  Divisor3 & !R0 & !R2
         #  Divisor1 &  Divisor3 & !R1 & !R2
         #  Divisor1 &  Divisor2 & !R1 & !R3
         #  Divisor1 & !R1 & !R2 & !R3;

-- Node name is '|arch:25|alu8:49|adder8:48|adder:30|~38~1' from file "adder.tdf" line 13, column 26
-- Equation name is '_LC104', type is buried 
-- synthesized logic cell 
_LC104   = LCELL( _EQ026 $  GND);
  _EQ026 =  Divisor0 &  Divisor3 & !R0 & !R1 & !R2
         #  Divisor0 &  Divisor1 &  Divisor2 & !R0 & !R3
         #  Divisor0 &  Divisor2 & !R0 & !R1 & !R3
         #  Divisor0 &  Divisor1 & !R0 & !R2 & !R3
         #  Divisor0 & !R0 & !R1 & !R2 & !R3;

-- Node name is '|arch:25|alu8:49|adder8:48|adder:30|:38' from file "adder.tdf" line 13, column 26
-- Equation name is '_LC072', type is buried 
!_LC072  = _LC072~NOT;
_LC072~NOT = LCELL( _EQ027 $  _EQ028);
  _EQ027 = !Divisor5 &  R5 &  _X014 &  _X015 &  _X016
         # !Divisor5 & !_LC102 & !_LC103 & !_LC104 &  R4 &  _X014 &  _X015 & 
              _X016
         # !Divisor4 & !Divisor5 &  R4 &  _X014 &  _X015 &  _X016
         # !Divisor4 & !Divisor5 & !_LC102 & !_LC103 & !_LC104 &  _X014 & 
              _X015 &  _X016;
  _X014  = EXP(!_LC102 & !_LC103 & !_LC104 &  R4 &  R5);
  _X015  = EXP(!Divisor4 &  R4 &  R5);
  _X016  = EXP(!Divisor4 & !_LC102 & !_LC103 & !_LC104 &  R5);
  _EQ028 =  _X014 &  _X015 &  _X016;
  _X014  = EXP(!_LC102 & !_LC103 & !_LC104 &  R4 &  R5);
  _X015  = EXP(!Divisor4 &  R4 &  R5);
  _X016  = EXP(!Divisor4 & !_LC102 & !_LC103 & !_LC104 &  R5);

-- Node name is '|arch:25|alu8:49|adder8:48|adder:34|~38~1' from file "adder.tdf" line 13, column 26
-- Equation name is '_LC125', type is buried 
-- synthesized logic cell 
_LC125   = LCELL( _EQ029 $  GND);
  _EQ029 =  Divisor7 & !R7
         #  Divisor4 &  Divisor5 & !R6 &  _X008
         #  Divisor5 & !R5 & !R6
         #  Divisor6 & !R6
         #  Divisor5 &  Divisor6 & !R5;
  _X008  = EXP(!_LC102 & !_LC103 & !_LC104);

-- Node name is '|arch:25|alu8:49|adder8:48|adder:34|~38~2' from file "adder.tdf" line 13, column 26
-- Equation name is '_LC119', type is buried 
-- synthesized logic cell 
_LC119   = LCELL( _EQ030 $  GND);
  _EQ030 =  Divisor5 & !R4 & !R6 &  _X008
         #  Divisor4 &  Divisor5 & !R4 & !R6
         #  Divisor4 & !R5 & !R6 &  _X008
         # !R4 & !R5 & !R6 &  _X008
         #  Divisor4 & !R4 & !R5 & !R6;
  _X008  = EXP(!_LC102 & !_LC103 & !_LC104);

-- Node name is '|arch:25|alu8:49|adder8:48|adder:34|~38~3' from file "adder.tdf" line 13, column 26
-- Equation name is '_LC116', type is buried 
-- synthesized logic cell 
_LC116   = LCELL( _EQ031 $  GND);
  _EQ031 =  Divisor4 &  Divisor5 &  Divisor6 &  _X008
         #  Divisor5 &  Divisor6 & !R4 &  _X008
         #  Divisor4 &  Divisor5 &  Divisor6 & !R4
         #  Divisor4 &  Divisor6 & !R5 &  _X008
         #  Divisor6 & !R4 & !R5 &  _X008;
  _X008  = EXP(!_LC102 & !_LC103 & !_LC104);

-- Node name is '|arch:25|alu8:49|adder8:48|adder:34|~38~4' from file "adder.tdf" line 13, column 26
-- Equation name is '_LC122', type is buried 
-- synthesized logic cell 
!_LC122  = _LC122~NOT;
_LC122~NOT = LCELL( _EQ032 $  GND);
  _EQ032 =  Divisor4 &  Divisor6 & !R4 & !R5
         #  _LC125
         #  _LC119
         #  _LC116;

-- Node name is '|arch:25|rq16:55|~207~1' from file "rq16.tdf" line 21, column 143
-- Equation name is '_LC111', type is buried 
-- synthesized logic cell 
!_LC111  = _LC111~NOT;
_LC111~NOT = LCELL( _EQ033 $  GND);
  _EQ033 = !Divisor0 & !R0
         # !_LC122 & !R0 &  _X006
         #  _LC081 &  _LC114 &  _LC121
         #  Divisor0 & !Divisor7 &  R0 &  R7
         #  Divisor0 &  _LC122 &  R0;
  _X006  = EXP(!Divisor7 &  R7);

-- Node name is '|arch:25|rq16:55|~207~2' from file "rq16.tdf" line 21, column 143
-- Equation name is '_LC110', type is buried 
-- synthesized logic cell 
_LC110   = LCELL( _EQ034 $  _EQ035);
  _EQ034 = !Divisor0 & !Divisor1 &  _LC081 &  _LC114 &  _LC121 &  R1
         #  _LC081 &  _LC114 &  _LC121 & !_LC122 &  R1 &  _X006
         # !Divisor1 &  _LC081 &  _LC114 &  _LC121 &  R0 &  R1
         #  Divisor0 &  Divisor1 &  _LC081 &  _LC114 &  _LC121 & !R0 &  R1;
  _X006  = EXP(!Divisor7 &  R7);
  _EQ035 =  _LC081 &  _LC114 &  _LC121 & !R1 &  _X004 &  _X017 &  _X018 & 
              _X019;
  _X004  = EXP(!_LC122 &  _X006);
  _X017  = EXP(!Divisor1 &  R0);
  _X018  = EXP(!Divisor0 & !Divisor1);
  _X019  = EXP( Divisor0 &  Divisor1 & !R0);
  _X006  = EXP(!Divisor7 &  R7);

-- Node name is '|arch:25|rq16:55|~207~3' from file "rq16.tdf" line 21, column 143
-- Equation name is '_LC100', type is buried 
-- synthesized logic cell 
_LC100   = LCELL( _EQ036 $ !R1);
  _EQ036 = !Divisor0 & !Divisor1
         # !_LC122 &  _X006
         # !Divisor1 &  R0
         #  Divisor0 &  Divisor1 & !R0;
  _X006  = EXP(!Divisor7 &  R7);

-- Node name is '|arch:25|rq16:55|~255~1' from file "rq16.tdf" line 23, column 34
-- Equation name is '_LC108', type is buried 
-- synthesized logic cell 
_LC108   = LCELL( _EQ037 $  GND);
  _EQ037 = !Divisor3 & !_LC062 &  _LC081 & !_LC090 &  _LC106 &  _LC114 & 
              _LC121 &  R3 &  _X004
         #  Divisor3 & !_LC062 &  _LC081 &  _LC090 &  _LC106 &  _LC114 & 
              _LC121 &  R3 &  _X004
         #  DIV & !_LC062 & !_LC106
         # !Divisor3 &  _LC081 &  _LC090 &  _LC114 &  _LC121 & !R3
         #  Divisor3 &  _LC081 & !_LC090 &  _LC114 &  _LC121 & !R3;
  _X004  = EXP(!_LC122 &  _X006);
  _X006  = EXP(!Divisor7 &  R7);

-- Node name is '|arch:25|rq16:55|~270~1' from file "rq16.tdf" line 24, column 143
-- Equation name is '_LC098', type is buried 
-- synthesized logic cell 
_LC098   = LCELL( _EQ038 $  _EQ039);
  _EQ038 =  Divisor3 & !_LC090 & !R3 &  _X005 &  _X020
         # !Divisor3 &  _LC090 & !R3 &  _X005 &  _X020
         #  Divisor3 &  _LC090 &  R3 &  _X004 &  _X005 &  _X020
         # !Divisor3 & !_LC090 &  R3 &  _X004 &  _X005 &  _X020;
  _X005  = EXP( _LC081 &  _LC114 &  _LC121);
  _X020  = EXP(!_LC122 & !R3 &  _X006);
  _X004  = EXP(!_LC122 &  _X006);
  _X006  = EXP(!Divisor7 &  R7);
  _EQ039 =  _X005 &  _X020;
  _X005  = EXP( _LC081 &  _LC114 &  _LC121);
  _X020  = EXP(!_LC122 & !R3 &  _X006);
  _X006  = EXP(!Divisor7 &  R7);

-- Node name is '|arch:25|rq16:55|~270~2' from file "rq16.tdf" line 24, column 143
-- Equation name is '_LC113', type is buried 
-- synthesized logic cell 
_LC113   = LCELL( _EQ040 $  GND);
  _EQ040 =  _LC081 &  _LC114 &  _LC121 & !_LC122 &  R4 &  _X006
         # !Divisor4 &  _LC081 & !_LC102 & !_LC103 & !_LC104 &  _LC114 & 
              _LC121 &  R4
         #  Divisor4 &  _LC081 &  _LC114 &  _LC121 &  R4 &  _X008
         #  Divisor4 &  _LC081 & !_LC102 & !_LC103 & !_LC104 &  _LC114 & 
              _LC121 & !R4 &  _X004
         # !Divisor4 &  _LC081 &  _LC114 &  _LC121 & !R4 &  _X004 &  _X008;
  _X006  = EXP(!Divisor7 &  R7);
  _X008  = EXP(!_LC102 & !_LC103 & !_LC104);
  _X004  = EXP(!_LC122 &  _X006);

-- Node name is '|arch:25|rq16:55|~291~1' from file "rq16.tdf" line 25, column 143
-- Equation name is '_LC068', type is buried 
-- synthesized logic cell 
_LC068   = LCELL( _EQ041 $  GND);
  _EQ041 = !_LC122 &  R5 &  _X006
         # !Divisor4 & !Divisor5 & !_LC102 & !_LC103 & !_LC104 &  R5
         # !Divisor4 & !Divisor5 &  R4 &  R5
         #  Divisor5 & !R4 &  R5 &  _X008
         # !Divisor5 & !_LC102 & !_LC103 & !_LC104 &  R4 &  R5;
  _X006  = EXP(!Divisor7 &  R7);
  _X008  = EXP(!_LC102 & !_LC103 & !_LC104);

-- Node name is '|arch:25|rq16:55|~291~2' from file "rq16.tdf" line 25, column 143
-- Equation name is '_LC073', type is buried 
-- synthesized logic cell 
_LC073   = LCELL( _EQ042 $  GND);
  _EQ042 = !_LC122 &  _X006
         #  Divisor4 &  Divisor5 & !R4
         # !Divisor4 & !Divisor5 & !_LC102 & !_LC103 & !_LC104
         # !Divisor5 & !_LC102 & !_LC103 & !_LC104 &  R4
         # !Divisor4 & !Divisor5 &  R4;
  _X006  = EXP(!Divisor7 &  R7);

-- Node name is '|arch:25|rq16:55|~291~3' from file "rq16.tdf" line 25, column 143
-- Equation name is '_LC079', type is buried 
-- synthesized logic cell 
_LC079   = LCELL( _EQ043 $  _EQ044);
  _EQ043 =  Divisor4 &  Divisor5 &  R5 &  _X008
         #  Divisor4 &  Divisor5 & !R4 &  R5
         #  _LC068;
  _X008  = EXP(!_LC102 & !_LC103 & !_LC104);
  _EQ044 = !_LC073 & !R5 &  _X021 &  _X022;
  _X021  = EXP( Divisor4 &  Divisor5 &  _X008);
  _X022  = EXP( Divisor5 & !R4 &  _X008);
  _X008  = EXP(!_LC102 & !_LC103 & !_LC104);

-- Node name is '|arch:25|rq16:55|~297~1' from file "rq16.tdf" line 25, column 34
-- Equation name is '_LC127', type is buried 
-- synthesized logic cell 
_LC127   = LCELL( _EQ045 $  GND);
  _EQ045 = !Divisor4 & !_LC062 & !_LC102 & !_LC103 & !_LC104 &  _LC106 & !R4 & 
              _X005
         # !_LC062 &  _LC106 & !_LC122 & !R4 &  _X005 &  _X006
         #  Divisor4 & !_LC062 &  _LC106 & !R4 &  _X005 &  _X008
         # !_LC062 & !_LC079 &  _LC081 &  _LC106 &  _LC114 &  _LC121;
  _X005  = EXP( _LC081 &  _LC114 &  _LC121);
  _X006  = EXP(!Divisor7 &  R7);
  _X008  = EXP(!_LC102 & !_LC103 & !_LC104);

-- Node name is '|arch:25|rq16:55|~318~1' from file "rq16.tdf" line 26, column 34
-- Equation name is '_LC126', type is buried 
-- synthesized logic cell 
_LC126   = LCELL( _EQ046 $  GND);
  _EQ046 =  Divisor6 & !Divisor7 & !_LC062 &  _LC072 &  _LC081 &  _LC106 & 
              _LC114 &  _LC121 &  R7
         #  Divisor6 & !_LC062 &  _LC072 &  _LC081 &  _LC106 &  _LC114 & 
              _LC121 &  _LC122
         # !_LC062 &  _LC079 &  _LC106 & !R6 &  _X005
         # !_LC062 & !_LC079 &  _LC106 &  R6 &  _X005
         #  DIV & !_LC062 & !_LC106 &  R6;
  _X005  = EXP( _LC081 &  _LC114 &  _LC121);

-- Node name is '|arch:25|rq16:55|~334~1' from file "rq16.tdf" line 27, column 34
-- Equation name is '_LC124', type is buried 
-- synthesized logic cell 
_LC124   = LCELL( _EQ047 $  GND);
  _EQ047 = !_LC062 &  _LC081 &  _LC106 &  _LC114 &  _LC121
         #  Divisor6 & !_LC062 & !_LC072 &  _LC106 & !R6
         # !Divisor6 & !_LC062 &  _LC072 &  _LC106 & !R6
         # !_LC062 &  _LC106 & !_LC122 & !R6 &  _X006;
  _X006  = EXP(!Divisor7 &  R7);

-- Node name is '|arch:25|up3:60|uc0' from file "up3.tdf" line 8, column 5
-- Equation name is '_LC081', type is buried 
_LC081   = TFFE(!_EQ048, GLOBAL( clock), !_EQ049,  VCC,  VCC);
  _EQ048 =  _LC062
         # !_LC106;
  _EQ049 =  DIV & !_LC062 & !_LC106;

-- Node name is '|arch:25|up3:60|uc1' from file "up3.tdf" line 8, column 5
-- Equation name is '_LC114', type is buried 
_LC114   = DFFE( _EQ050 $  GND, GLOBAL( clock), !_EQ051,  VCC,  VCC);
  _EQ050 = !_LC106 &  _LC114
         #  _LC062 &  _LC114
         # !_LC062 &  _LC081 &  _LC106 & !_LC114
         # !_LC081 &  _LC114;
  _EQ051 =  DIV & !_LC062 & !_LC106;

-- Node name is '|arch:25|up3:60|uc2' from file "up3.tdf" line 8, column 5
-- Equation name is '_LC121', type is buried 
_LC121   = TFFE( _EQ052, GLOBAL( clock), !_EQ053,  VCC,  VCC);
  _EQ052 = !_LC062 &  _LC081 &  _LC106 &  _LC114;
  _EQ053 =  DIV & !_LC062 & !_LC106;

-- Node name is '|control:26|ss~1' from file "control.tdf" line 23, column 3
-- Equation name is '_LC062', type is buried 
_LC062   = TFFE( _EQ054, GLOBAL( clock), !RESET,  VCC,  VCC);
  _EQ054 =  DIV & !Divisor0 & !Divisor1 & !Divisor2 & !Divisor3 & !Divisor4 & 
             !Divisor5 & !Divisor6 & !Divisor7 & !_LC062 & !_LC106
         # !DIV &  _LC062 & !_LC106
         # !_LC062 &  _LC081 &  _LC106 &  _LC114 &  _LC121;

-- Node name is '|control:26|ss~2' from file "control.tdf" line 23, column 3
-- Equation name is '_LC106', type is buried 
_LC106   = DFFE( _EQ055 $  VCC, GLOBAL( clock), !RESET,  VCC,  VCC);
  _EQ055 =  _LC062 & !_LC106
         # !DIV & !_LC106
         # !_LC062 &  _LC081 &  _LC106 &  _LC114 &  _LC121;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X004 occurs in LABs -----FGH
--    _X005 occurs in LABs -----FGH
--    _X006 occurs in LABs ----EFGH
--    _X007 occurs in LABs -----F-H
--    _X008 occurs in LABs ----E--H




Project Informationj:\odu\ece\ece 341\project\website\current\components\divider.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic I/O Cell Registers        = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 0

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = CUSTOM
Smart Recompile                           = off
Total Recompile                           = off

Interface Menu Commands
-----------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:01:15
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:01:18


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,362K
