341 Project Team Website

Team Design Modules Characteristics: TS = 9 clock cycles by 35% chip utilization = 315 The details can be found in the divider.rpt file generated by MAX+plus 2 Team's Divider (Updated 4/22/1998) Explodable Design Tour (Updated 4/30/1998) Control Unit ASM Chart (Updated 4/22/1998) Components (Updated 4/22/1998) Evolution of Design Start with the ASM provided in class Constructed an ASM diagram from algorithm described in handout. Verified example problem from handout Decided on a control unit / architecture separation Determined architecture components 8-bit register for divisor 16-bit shift register for remainder and quotient 3-bit counter (8-bit word width) ALU (use 2's complement for subtraction) Looked into using a carry look ahead adder instead of a ripple carry adder Included the initial LEFT shift into the preload of the RQ16 register Store the old value instead of adding back the divisor First tried to design a separate register to hold the old data Settled on including in logic of RQ16 register Refined the RQ16 register to load appropriately shifted values based on the ALU carry out values. Included the final RIGHT shifting of the remainder (R) into the RQ16 register logic. Resources ECE 341 Design Project description Dr. Meyer's "official" webpage describing project. (Local copy archived from source on 4/24/1998) Includes: Problem specification Design constraints and goals Design phase Simulation phase Demonstration and reporting requirements Grading Task List, last updated 3/20/98 Includes notes from the first group discussion Arithmetic for Computers -- Division, (502 KB .pdf) Handout given to each team describing three division algorithms. Source unknown. Altera, developers of MAX+PLUS 2 Software Feature references provided by Altera. MAX+PLUS II Programmable Logic Development System & Software Data Sheet, ver. 8, (381 KB .pdf) MAX+PLUS II Getting Started version 8.1, (5.4 MB .pdf) Send mail to team members: Del Croom Samaria Hunter Loreyna Yeung Last modified 4/30/1998