- 16-bit Modified Shift Register
- 3-bit Up Counter
- 8-bit Register
- 8-bit Adder/Subtracter (ALU)
- 8-bit Ripple Carry Adder Unit
- 1-bit Adder Unit
- ALU using carry look-ahead logic (too big to fit on chip)
Architecture Design
Architecture Implementation
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General Overview of Architecture:
- 16-bit Modified Shift Register (updated 4/13/1998)
- Characteristics:
Remainder is computed in high byte, quotient is computed in low byte. ALU feeds the high byte. Remainder only needs to be shifted right to obtain the correct answer at the end of the algorithm.
- clk -- clock, rising edge
- RQ_LOAD -- clears high byte of RQ, loads low byte of RQ with Dividend, preshift left one bit (saves step 1)
- LEFT -- shifts RQ left, loading in value on Q_IN
- LD_R -- latches ALU results into high byte of RQ
- RIGHT -- shifts high byte only to the right (loads a zero)
- Data Inputs -- Dividend[7..0], ALU[7..0]
- Data Outputs -- R ( RQ[15..8]) and Q ( RQ[7..0] )
MaxPlus+2 Files Symbol AHDL source 
Simulation source Report file Symbol file 
- [ Contents ] [ Design ] [ Implementation ]
- 3-bit Up Counter (updated 4/11/1998)
- 3-bit Up Counter (updated 4/11/1998)
- Characteristics:
3-bit up counter is used to track the shifting of the dividend. Since the architecture is clocked on the same edge as the C/U, the output O7 is monitored.
- clk -- clock, rising edge
- CNT_CLR -- clears counter
- UP -- increments counter
- Data Outputs -- C[2..0]
MaxPlus+2 Files Symbol AHDL source 
Simulation source Report file Symbol file 
- [ Contents ] [ Design ] [ Implementation ]
- 8-bit Register (updated 4/11/1998)
- 8-bit Register (updated 4/11/1998)
- Characteristics:
8-bit register is used to hold the divisor, which is used by the ALU as the "constant" input which is repeatedly subtracted (or added).
- clk -- clock, rising edge
- LD_D -- loads register
- Data Inputs -- Din[7..0]
- Data Outputs -- D[7..0]
MaxPlus+2 Files Symbol AHDL source 
Simulation source Report file Symbol file 
- [ Contents ] [ Design ] [ Implementation ]
- 8-bit Adder/Subtracter (ALU) (updated 4/13/1998)
- 8-bit Adder/Subtracter (ALU) (updated 4/13/1998)
- Characteristics:
8-bit add/subtracter (ALU) is used to perform addition and subtraction of 8-bit numbers. This unit uses two level logic for the 1-bit adders and ripple carry between units. (see 8-bit carry look-ahead unit and the 1-bit adder unit below for details of an alternate design that is faster but cannot fit on the chip.) There are no provisions for overflow or underflow correction.
- A/S -- adds inputs (low) or subtracts (high)
- Data Inputs -- X[7..0], Y[7..0]
- Data Outputs -- S[7..0]
MaxPlus+2 Files Symbol Graphics editor file 
Simulation source Report file Symbol file 
Maximum Propagation Delay 
- [ Contents ] [ Design ] [ Implementation ]
- 8-bit Adder unit (updated 4/13/1998)
- 8-bit Adder unit (updated 4/13/1998)
- Characteristics:
A component of the 8-bit ALU. It is composed of eight 1-bit adder units serially connected to form an 8-bit ripple carry adder bit used by the ALU.
- Data Inputs -- X[7..0], Y[7..0], A/S (high when used to subtract, Cin term)
- Data Outputs -- S[7..0], Cout
MaxPlus+2 Files Symbol Graphics editor file 
Simulation source Report file Symbol file 
- [ Contents ] [ Design ] [ Implementation ]
- 1-bit Adder unit (updated 4/11/1998)
- 1-bit Adder unit (updated 4/11/1998)
- Characteristics:
A component of the 8-bit ALU. The 1-bit adder is used to determine the sum bit and the carry bit used by the ALU. It uses two-level logic and participates in a ripple carry configuration. (Reference Nelson(1995), pp 313.)
- Data Inputs -- A, B, Cin
- Data Outputs -- S, Cout
MaxPlus+2 Files Symbol Graphics editor file 
Simulation source Report file Symbol file 
- [ Contents ] [ Design ] [ Implementation ]
- This design does not fit on the chip, but is provided for reference.
- 8-bit Adder/Subtracter (ALU) (using carry look-ahead logic, updated 4/11/1998)
- Characteristics:
8-bit add/subtracter (ALU) is used to perform addition and subtraction of 8-bit numbers. This unit used a carry look-ahead adder to reduce the ripple carry delay time. (see 8-bit carry look-ahead unit and the 1-bit adder unit below for details.) The Y vector holds the Divisor (which gets complemented for addition). There are no provisions for overflow or underflow detection or correction.
- A/S -- adds inputs (low) or subtracts (high)
- Data Inputs -- X[7..0], Y[7..0]
- Data Outputs -- D[7..0]
MaxPlus+2 Files Symbol Graphics editor file Simulation source Report file Symbol file Does not fit on chip - [ Contents ] [ Design ] [ Implementation ]
- 8-bit Carry Look-ahead Adder (updated 4/10/98)
- 8-bit Carry Look-ahead Adder (updated 4/10/98)
- Characteristics:
A component of the 8-bit ALU. The 8-bit carry look-ahead adder (CLA) is used to perform addition and subtraction of 8-bit numbers using 2 level logic to determine the carry terms. The carrys are computed simultaneously to obliviate the ripple carry delays found in the basic design presented in ECE 241. (Reference Nelson(1995), pp 290-291.)
- Data Inputs -- A[7..0], B[7..0], Cin
- Data Outputs -- S[7..0], Cout
MaxPlus+2 Files Symbol Graphics editor file 
Simulation source Report file Symbol file No waveform available (output not intuitive) - [ Contents ] [ Design ] [ Implementation ]
- 1-bit Adder unit (updated 4/10/98)
- 1-bit Adder unit (updated 4/10/98)
- Characteristics:
A component of the 8-bit ALU. The 1-bit adder is used to determine the sum bit and the coefficients used by the CLA unit to generate the carry terms. (Reference Nelson(1995), pp 290-291.)
- Data Inputs -- A, B, Cin
- Data Outputs -- P, Q, S
MaxPlus+2 Files Symbol Graphics editor file 
Simulation source Report file Symbol file 
Symbol:
[ Contents ] [ Design ] [ Implementation ]
Created 4/10/1998
Last modified 4/22/1998