The external inputs to your division circuit are the numbers A and B, an input called RESET, and an input called DIV. RESET can be used to reset your control circuit to its initial state, and to reset various architectural components. When DIV is asserted, the A and B inputs are divided. The outputs from your divider are Q, R, ERROR, and DONE. When a valid result, (Q, R), is ready at the dividers output, an output called DONE should be asserted. The result (Q, R) should be held valid until DIV is deasserted and subsequently reasserted (After the DIV button is pressed, (Q, R) should remain valid until the button is released and pressed the next time). If a divide by zero error is detected, the ERROR output should be asserted.

In designing your division circuit, your design primary design goal should be to minimize computation time and chip utilization. In particular, design your circuit in order to minimize the time-size product shown below. 

Your success at minimizing this design constraint will be evaluated on a competitive basis. All working designs will be ranked smallest TS to largest TS, and a number of grade points (from a maximum of 15 down to a minimum of 0) will be assigned. Working designs will be ranked above non-working designs (a small fast chip that doesn't work is of limited value).

Note: An efficient design is the most effective way to minimize TS. There are many different ways to reduce chip utilization, including experimenting with the various compiler settings within MaxPlus+2. We will probably not discuss these settings in class, however they are described in the online documentation associated with the MaxPlus+2 help menus.

For this project, you are not allowed to use any pre-designed components from MaxPlus+2's extensive libraries. You must use AHDL to separately design, simulate, and create symbols for each individual component of your system. You can then use the graphical editor to combine these components to form the complete divider circuit. You may not design your divider as a strictly combinational circuit, or by using a ROM.

Use sound top-down design methodology to design your division circuit. Start by constructing a block diagram of your design. Clearly show the separation between architecture and controller. Show all external inputs to the system, as well as system outputs. Construct a detailed block diagram of your architecture. Create an ASM chart which describes your controller design, and implement it using a method of your choice.

Use the MaxPlus+2 design tool to compile and simulate your design. The target device for your design should be the Altera EPM7128SLC84-7 FPGA chip.

Your simulation should be carefully constructed, and comprehensive enough to convince you (and me) that your circuit will work reliably. Your simulation should illustrate a sufficient number of test cases to accurately demonstrate your circuit's:

• ability to accurately divide unsigned integers
• ability to handle divide-by-zero errors
• worst case computation time

Each team will demonstrate their final results to me during the week of April 20-24 (or before). Demonstration times will be scheduled on a first-come first-served basis. This demo, which should last approximately 30 minutes, will consist of an oral presentation of your design strategy, and a demonstration of your simulation. For your oral presentation, please prepare a 15 minute explanation of your results which specifically addresses the following items, as well as any others you wish to discuss:

• Division algorithm used, and how it has been implemented in circuitry.
• Overall performance (does it work?, bugs not yet fixed, etc.)
• Chip utilization. Techniques used to keep chip utilization to a minimum.
• Worst case computation time. An honest and accurate assessment of your circuit's worst case speed.
• Breakdown of tasks (who did what).

Your report should also contain your analysis and computation of TS. This analysis of your divider's performance must be honest and accurate - I will check it carefully, and points will be deducted if you have mistakenly overestimated your circuit's performance.