General Notes:
- Target completion date: Friday, April 17, 1998
Algorithm Selection
Each of us is to find one other division algorithm and report back to the team by Friday, March 27
For each algorithm investigated:
- Citation
- Description
- ASM Chart
- Architecture / Control Unit (A/CU) preliminary design
- A/CU component list
- Advantages
- Disadvantages
For each algorithm that holds promise:
Component Development
Decided on 3/20 to proceed with development of components needed to implement the algorithm discussed in the handout, which include:
- Shift left register, 16-bit (Remainder)
- Register, 8-bit (Divisor)
- Adder/Subtractor, 8-bit (ALU)
- May be able to substitute an 8-bit register for the addition function.
- Down counter, 3-bit (final decision diamond in ASM, check 8 shifts)
- Zero checker, 3-input NAND gate
This activity will include
- Logic design
- AHDL coding
- MaxPlus+2 simulation
- Design verification
- Timing characteristics
- Resource usage
- Symbol creation
- Literature search for other designs ?
Component files should be distributed to the rest of the team for peer review/testing. A separate webpage will be devoted to archiving member contributions.
Architecture Integration
- MaxPlus+2 graphical editor design
- MaxPlus+2 simulation
- Design verification
- Timing characteristics
- Resource usage
- Symbol creation
Control Unit Development
- AHDL coding
- MaxPlus+2 simulation
- Design verification
- Timing characteristics
- Resource usage
- Symbol creation
A/CU Integration
- MaxPlus+2 graphical editor design
- MaxPlus+2 simulation
- Design verification
- Timing characteristics
- Resource usage
- Symbol creation
Components with the same design characteristics may be reused. However, we need to be mindful that each programmer has a unique perspective that may contribute unforseen efficiencies to current designs.
Optimization
Once convinced of an efficient design, the MaxPlus+2 environment must be explored to determine the optimal inplementation parameters.
Demonstration
Agenda:
- Design algorithm used
- Description
- How implemented
- Overall performance
- Chip utilization
- % utilization
- Techniques used to minimize
- Worst case computation time
- Clock cycles
- How determined
- Breakdown of tasks
- Demonstration (simulation waveforms)
- Generic case, to demonstrate algorithm
- Extreme cases, to test correctness of algorithm
- Divide by zero
- Divide into zero
- Full 8-bit quotient
- No quotient
- 7-bit remainder
- No remainder
- Worst case demonstration
Report
- Description of algorithm used
- Detailed architectural block diagram
- Controller ASM
- Design of individual system components
- Analysis and computation of time-size product (TS)
Last modified 3/20/98